Design and Research of Improved Digital Phase-Locked Loop Based on FPGA

Design and Implementation of FPGA based linear All Digital Phase-Locked Loop for Signal Processing Applications

Digital Phase - Locked Loop Based on FIR Filters

In this paper, a new digital phase-locked loop (DPLL) is proposed based on finite impulse response (FIR) filters. The proposed DPLL is more robust to incorrect noise information than the existing DPLL using fixed gain. We show the effectiveness of the proposed DPLL via a numerical example.

Fuzzy logic for digital phase-locked loop filter design

The problem of robust phase-locked loop design has attracted attention for many years, particularly since the advent of the global positioning system. This paper proposes and demonstrates the use of a fuzzy PLL to estimate the time-varying phase of a sinusoidal signal. It is shown via simulation results that fuzzy PLL's offer performance comparable to analytically derived PLL's (e.g. Kalman fil...

Phase-Locked Loop Design Fundamentals

The fundamental design concepts for phase-locked loops implemented with integrated circuits are outlined. The necessary equations required to evaluate the basic loop performance are given in conjunction with a brief design example. NOTE This document contains references to obsolete part numbers and is offered for technical information only.

Design and Simulation of a Modified 32-bit ROM-based Direct Digital Frequency Synthesizer on FPGA

This paper presents a modified 32-bit ROM-based Direct Digital Frequency Synthesizer (DDFS). Maximum output frequency of the DDFS is limited by the structure of the accumulator used in the DDFS architecture. The hierarchical pipeline accumulator (HPA) presented in this paper has less propagation delay time rather than the conventional structures. Therefore, it results in both higher maximum ope...